The present subject matter relates to a semiconductor device, and more particularly, to a detector for detecting skew information according to process, voltage and temperature, and a delay locked loop (DLL) that can guarantee an initial delay time using the detector, regardless of process, voltage, and temperature (PVT).
Generally, semiconductor memory devices such as a double data rate synchronous dynamic random access memory (DDR SDRAM) are designed to receive an external clock (CLK_EXT) to generate an internal clock (CLK_INN). The internal clock (CLK_INN) is used as a reference for adjusting an operation timing. Therefore, clock synchronization circuits are used for synchronizing the timing of the external clock (CLK_EXT) with that of the internal clock (INN). Examples of the clock synchronization circuits include a phase locked loop (PLL) and a delay locked loop (DLL).
The PLL having a frequency multiplication function is widely used when the frequency of the external clock (CLK_EXT) is different from that of the internal clock (CLK_INN). The DLL is widely used when the frequency of the external clock (CLK_EXT) is equal to that of the internal clock (CLK_INN). The PLL has a structure similar to that of the DLL. However, the PLL uses a voltage controlled oscillator (VCO) to generate the internal clock (CLK_INN), while the DLL uses a voltage controlled delay line (VCDL).
A semiconductor memory device includes a very large number of resistors, capacitors, and transistors. The semiconductor memory device performs a variety of operations according to combinations of the resistors, the capacitors, and the transistors.
PVT characteristics of the resistors, the capacitors, and the transistors may vary with process, voltage, and temperature. Especially, the operating speeds of the capacitors and the transistors may vary according to the PVT characteristics. Due to the PVT characteristics, PVT skew may be caused in the semiconductor memory device.
FIG. 1 is a block diagram of a conventional DLL.
Referring to FIG. 1, the conventional DLL includes a phase detector 110, a control voltage generator 130, a voltage controlled delay line 150, and a delay replica model 170.
The phase detector 110 detects a phase difference between an external clock CLK_EXT and a feedback clock CLK_FED to output an up detection signal DET_UP or a down detection signal DET_DN. The up detection signal DET_UP and the down detection signal DET_DN are pulse signals having pulse widths corresponding to the phase difference between the external clock CLK_EXT and the feedback clock CLK_FED.
The control voltage generator 130 outputs a voltage control signal V_CTR having a voltage level corresponding to the up detection signal DET_UP or the down detection signal DET_DN. The voltage level of the voltage control signal V_CTR increases in response to the up detection signal DET_UP but decreases in response to the down detection signal DET_DN.
The voltage controlled delay line 150 generates an internal clock CLK_INN by reflecting a delay time corresponding to the voltage control signal V_CTR on the external clock CLK_EXT. A short delay time is reflected on the external clock CLK_EXT when the voltage level of the voltage control signal V_CTR is high, and a long delay time is reflected on the external clock CLK_EXT when the voltage level of the voltage control signal V_CTR is low.
The delay replica model 170 outputs the feedback clock CLK_FED by reflecting a delay time of an actual clock/data path on the internal clock CLK_INN.
Upon operation, the DLL detects the phase difference between the external clock CLK_EXT and the feedback clock CLK_FED to generate the voltage control signal V_CTR corresponding to the detected phase difference. Then, the DLL outputs the internal clock CLK_INN by reflecting the delay time corresponding to the voltage control signal V_CTR on the external clock CLK_EXT. The DLL repeats these operations until the external clock CLK_EXT has the same phase as the feedback clock CLK_FED, and finally generates the desired internal clock CLK_INN.
FIG. 2 is a circuit diagram of the voltage controlled delay line 150 illustrated in FIG. 1.
Referring to FIG. 2, the voltage controlled delay line 150 includes a plurality of delay cells 210, 230, 250 and 270 configured to reflect the delay time corresponding to the voltage control signal V_CTR on the external clock CLK_EXT.
For convenience, a reference symbol “CLK_EXT” is used to refer to a positive external clock having the same phase as the external clock CLK_EXT. A negative external clock /CLK_EXT is a clock having a phase opposite to the positive external clock CLK_EXT. Because the DLL simultaneously receives the positive external clock CLK_EXT and the negative external clock /CLK_EXT, the phase detector 110 can compare the phase difference ranging from 0 to π, not from 0 to 2π.
The first to fourth delay cells 210, 230, 250 and 270 reflect the delay time corresponding to the voltage control signal V_CTR on the input signal. The delay time becomes shorter as the voltage level of the voltage control signal V_CTR becomes higher, and becomes longer as the voltage level of the voltage control signal V_CTR becomes lower. Consequently, a rising internal clock RCLK_INN is outputted after the delay time is reflected on the positive external clock CLK_EXT through the first to fourth delay cells 210, 230, 250 and 270, and a falling internal clock FCLK_INN is outputted after the delay time is reflected on the negative external clock /CLK_EXT through the first to fourth delay cells 210, 230, 250 and 270.
In other words, the voltage controlled delay line 150 of the DLL receives the positive external clock CLK_EXT and the negative external clock /CLK_EXT to output the rising internal clock RCLK_INN and the falling internal clock FCLK_INN. Because the phase detector 110 compares the positive external clock CLK_EXT with the feedback clock CLK_FED generated by reflecting the delay time of the delay replica model 170 on the falling internal clock FCLK_INN, it can compare the phase difference ranging from 0 to π, not from 0 to 2π.
FIG. 3 is a circuit diagram of the first delay cell 210 illustrated in FIG. 2. Since the first to fourth delay cells 210, 230, 250 and 270 have the similar structure, only the structure of the first delay cell 210 will be described below.
The first delay cell 210 includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first symmetrical load 310, a second symmetrical load 330, and a third NMOS transistor NM3. The first NMOS transistor NM1 has a source and a drain connected between a first output terminal /OUT and a first node N1, and a gate receiving the positive external clock CLK_EXT. The second NMOS transistor NM2 has a source and a drain connected between a second output terminal OUT and the first node N1, and a gate receiving the negative external clock /CLK_EXT. The first symmetrical load 310 is connected between an external voltage terminal VDD and the first output terminal /OUT, and the second symmetrical load 330 is connected between the external voltage terminal VDD and the second output terminal OUT. The third NMOS transistor NM3 has a source and a drain connected between the first node N1 and a ground terminal VSS, and a gate receiving a bias voltage V_BIAS.
Each of the first and second symmetrical loads 310 and 330 includes two PMOS transistors. One of the two PMOS transistors has a gate receiving the voltage control signal V_CTR and controls a current flowing through the first and second output terminals /OUT and OUT. A delay time of the first delay cell 210 is determined according to the currents flowing through the first and second output terminals /OUT and OUT.
The positive external clock CLK_EXT and the negative external clock /CLK_EXT are outputted as the rising internal clock RCLK_INN and the falling internal clock FCLK_INN after the delay time reflected in the first to fourth delay cells 210, 230, 250 and 270.
Meanwhile, it should be noticed that the initial delay time must be secured in designing the voltage controlled delay line 150. The initial delay time is a delay time that the voltage controlled delay line 150 must have in an initial operation of the DLL. The initial delay time of the voltage controlled delay line 150 will be described below with reference to FIG. 4.
FIG. 4 is a graph of an operation characteristic of the phase detector 110 illustrated in FIG. 1.
In FIG. 4, a horizontal axis represents a phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED, and a horizontal axis represents a pulse width of the up detection signal DET_UP and a pulse width of the down detection signal DET_DN. As the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED becomes larger, the pulse width of the up detection signal DET_UP becomes longer and thus the delay time of the voltage controlled delay line 150 decreases. Hence, the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED is reduced.
A region indicated by a dotted line is a dead zone where the phase detector 110 does not operate. The dead zone is formed near a region where the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED is −π, 0 and π. The phase detector 110 does not operate when the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED falls within the dead zone in the initial operation. Thus, the designer must appropriately set the initial delay time of the voltage controlled delay line 150 so that the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED cannot fall within the dead zone.
FIGS. 5A and 5B are timing diagrams of the initial delay time.
More specifically, FIG. 5A shows a case where the voltage controlled delay line 150 normally obtains the desired initial delay time INT_N.
In this case, the phase difference between the rising edge of the feedback clock CLK_FED and the rising edge of the positive external clock CLK_EXT does not fall within the dead zone because the initial delay time INT_N is sufficiently guaranteed. The DLL performs a normal operation to synchronize the rising edge of the feedback clock CLK_FED with the rising edge of the positive external clock CLK_EXT.
FIG. 5B shows a case where the voltage controlled delay line 150 abnormally obtains the initial delay time INT_A.
In this case, the phase difference between the rising edge of the feedback clock CLK_FED and the rising edge of the positive external clock CLK_EXT is approximately π. This phase difference causes the malfunction of the phase detector 110. In serious cases, the phase detector 110 does not operate. This is called an initial lock fail of the DLL.
Meanwhile, each of the first to fourth delay cells 210, 230, 250 and 270 of the voltage controlled delay line 150 includes a plurality of transistors as illustrated in FIG. 3. Therefore, PVT skew may occur according to process, voltage and temperature. This means that the initial delay time of the voltage controlled delay line 150 becomes longer or shorter than the designer intends.
For convenience, the PVT characteristics will be classified into “TYPICAL”, “FAST”, and “SLOW”.
“TYPICAL” refers to a case where the operating speeds of the NMOS transistor and the PMOS transistor are typical, “FAST” refers to a case where the operating speeds of the NMOS transistor and the PMOS transistor are faster than the TYPICAL case due to the PVT characteristics, and “SLOW” refers to a case where the initial delay time is longer than intended.
When the PVT characteristics are “TYPICAL”, the voltage controlled delay line 150 provides the initial delay time intended by the designer. When the PVT characteristics are “FAST”, the initial delay time become shorter than intended. When the PVT characteristics are “SLOW”, the initial delay time becomes longer than intended.
In other words, when the PVT characteristics are “FAST”, the initial delay time cannot be sufficiently guaranteed as illustrated in FIG. 5B. Therefore, the phase difference between the feedback clock CLK_FED and the positive external clock CLK_EXT falls within the dead zone. Thus, the initial lock fail of the DLL may occur. On the other hand, when the PVT characteristics are “SLOW”, the initial delay time becomes too long, the phase difference between the feedback clock CLK_FED and the positive external clock CLK_EXT also falls within the dead zone. Consequently, the initial lock fail of the DLL may occur.